[OpenSCAD] ClikScad - create OpenSCAD models without all the typing

Torsten Paul Torsten.Paul at gmx.de
Fri Oct 25 15:49:21 EDT 2019

On 25.10.19 15:50, nop head wrote:
> The problem is it is too sparse because typically one
> line of code becomes a box. So what happens to a design
> that is 350 lines?

Not necessarily. Maybe a more sensible comparison would
be ICEStudio https://github.com/FPGAwars/icestudio which
can create blocks for whole Verilog modules.


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